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CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 1 doc. no. 1125 rev. a characteristics subject to change without notice voltage supervisor with 8-kb and 16-kb spi serial cmos eeprom features ? precision power supply voltage monitor ? 5v, 3.3v, 3v & 2.5v systems ? 7 threshold voltage options ? active high or low reset ? valid reset guaranteed at v cc = 1v ? 10mhz spi compatible ? 32-byte page write buffer ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? rohs-compliant 8-pin soic package for ordering information details, see page 14. pin configuration soic (w) cs 1 8 v cc so 2 7 rst/ rst wp 3 6 sck v ss 4 5 si description the CAT15008/16 (see table below) are memory and supervisory solutions for mi crocontroller based systems. a cmos serial eeprom memo ry and a system power supervisor with brown-out protection are integrated together. memory interface is via spi bus serial interface. the CAT15008/16 provides a precision v cc sense circuit with two reset output options: cmos active low output or cmos active high. the reset output is active whenever v cc is below the reset threshold or falls below the reset threshold voltage. the power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. seven reset threshold voltages support 5v, 3.3v, 3v and 2.5v systems. if power supply voltages are out of tolerance reset signals become active, preventing t he system microcontroller, asic or peripherals from operating. reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level. memory size selector product memory density 15008 8-kbit 15016 16-kbit pin function pin name function cs chip select so serial data output wp write protect v ss ground si serial data input sck serial clock input rst/ rst reset output v cc power supply threshold suffix selector nominal threshold voltage threshold suffix designation 4.63v l 4.38v m 4.00v j 3.08v t 2.93v s 2.63v r 2.32v z
CAT15008, cat15016 doc. no. 1125 rev. a 2 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice block diagram absolute maximum ratings (1) parameters ratings units storage temperature -65 to +150 c voltage on any pin with respect to ground (2) -0.5 to +6.5 v reliability characteristics (3) symbol parameter min units nend (4) endurance 1,000,000 program/ erase cycles tdr data retention 100 years d.c. operating characteristics v cc = +2.5v to +5.5v unless otherwise specified. limits symbol parameter min. typ. max. test condition units i cc supply current 2 read or write at 10mhz, so open ma 12 25 v cc < 5.5v; v in = v ss or v cc , cs = v cc i sb standby current 10 20 v cc < 3.6v; v in = v ss or v cc , cs = v cc a i l i/o pin leakage 2 pin at gnd or v cc a v il input low voltage -0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage 0.4 v cc 2.5v, i ol = 3.0ma v v oh output high voltage v cc - 0.8 v cc 2.5v, i oh = -1.6ma v notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc + 0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc + 1.5v, for periods of less than 20ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods. (4) page mode, v cc = 5v, 25c so eeprom sck si cs wp v cc voltage detector rst or rs t v ss
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 3 doc. no. 1125 rev. a characteristics subject to change without notice a.c. characteristics (memory) (1) v cc = 2.5v to 5.5v, t a = -40c to 85c, unless otherwise specified. symbol parameter min. max. units f sck clock frequency dc 10 mhz t su data setup time 20 ns t h data hold time 20 ns t wh sck high time 40 ns t wl sck low time 40 ns t lz hold to output low z 25 ns t ri (2) input rise time 2 s t fi (2) input fall time 2 s t hd hold setup time 0 ns t cd hold hold time 10 ns t v output valid from clock low 40 ns t ho output hold time 0 ns t dis output disable time 20 ns t hz hold to output high z 25 ns t cs cs high time 15 ns t css cs setup time 15 ns t csh cs hold time 15 ns t wps wp setup time 10 ns t wph wp hold time 10 ns t wc (4) write cycle time 5 ms t pu (2) (3) power-up to ready mode 1 ms notes : (1) test conditions according to ?a.c. test conditions? table. (2) tested initially and after a design or pr ocess change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. (4) t wc is the time from the rising edge of cs after a valid write sequence to the end of the internal write cycle. a.c. test conditions input rise and fall times 10ns input levels 0.3 v cc to 0.7 v cc timing reference levels 0.5 v cc output load current source: i ol max/ i oh max; c l = 50pf
CAT15008, cat15016 doc. no. 1125 rev. a 4 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice electrical characteristic s (supervisory function) v cc = full range, t a = -40oc to +85oc unless otherw ise noted. typical values at t a = +25oc and v cc = 5v for l/m/j versions, v cc = 3.3v for t/s versions, v cc = 3v for r version and v cc = 2.5v for z version. symbol parameter threshold conditions min typ max units t a = +25oc 4.56 4.63 4.70 l t a = -40oc to +85oc 4.50 4.75 t a = +25oc 4.31 4.38 4.45 m t a = -40oc to +85oc 4.25 4.50 t a = +25oc 3.93 4.00 4.06 j t a = -40oc to +85oc 3.89 4.10 t a = +25oc 3.04 3.08 3.11 t t a = -40oc to +85oc 3.00 3.15 t a = +25oc 2.89 2.93 2.96 s t a = -40oc to +85oc 2.85 3.00 t a = +25oc 2.59 2.63 2.66 r t a = -40oc to +85oc 2.55 2.70 t a = +25oc 2.28 2.32 2.35 v th reset threshold voltage z t a = -40oc to +85oc 2.25 2.38 v symbol parameter conditions min typ (1) max units reset threshold tempco 30 ppm/oc t rpd v cc to reset delay (2) v cc = v th to (v th -100mv) 20 s t purst reset active timeout period t a = -40oc to +85oc 140 240 460 ms v cc = v th min, i sink = 1.2ma r/s/t/z 0.3 v cc = v th min, i sink = 3.2ma j/l/m 0.4 v ol reset output voltage low (push-pull, active low, cat150xx9) v cc > 1.0v, i sink = 50a 0.3 v v cc = v th max, i source = -500a r/s/t/z 0.8v cc v oh reset output voltage high (push-pull, active low, cat150xx9) v cc = v th max, i source = -800a j/l/m v cc - 1.5 v v cc > v th max, i sink = 1.2ma r/s/t/z 0.3 v ol reset output voltage low (push-pull, active high, cat150xx1) v cc > v th max, i sink = 3.2ma j/l/m 0.4 v v oh reset output voltage high (push-pull, active high, cat150xx1) 1.8v < v cc v th min, i source = -150a 0.8v cc v notes : (1) production testing done at t a = +25oc; limits over temperature guaranteed by design only. (2) reset output for the cat150xx9; reset output for the cat150xx1.
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 5 doc. no. 1125 rev. a characteristics subject to change without notice pin description reset/ reset : reset output is available in two versions: cmos active low (cat150xx9) and cmos active high (cat150xx1). both versions are push-pull outputs for high efficiency. si: the serial data input pin accepts op-codes, addresses and data. in spi modes (0,0) and (1,1) input data is latched on the rising edge of the sck clock input. so: the serial data output pin is used to transfer data out of the device. in spi modes (0,0) and (1,1) data is shifted out on the falling edge of the sck clock. sck: the serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT15008/16. cs : the chip select input pin is used to enable/disable the CAT15008/16. when cs is high, the so output is tri-stated (high impedance) and the device is in standby mode (unless an internal write operation is in progress). every communication session between host and CAT15008/16 must be preceded by a high to low transition and concluded with a low to high transition of the cs input. wp : the write protect inpu t pin will allow all write operations to the device when held high. when wp pin is tied low and the wpen bit in the status register (refer to status r egister description, later in this data sheet) is set to ?1?, writing to the status register is disabled. device operation the CAT15008/16 products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard eeproms from catalyst semiconductor. reset controller description the reset signal is asserted low for the cat150xx9 and high for the cat150xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140ms (t purst ) after the power supply voltage has risen above the threshold. reset output timing is shown in figure 1. the CAT15008/16 devices protect ps against brown-out failure. short duration v cc transients of 4sec or less and 100mv amplitude typically do not generate a reset pulse. v cc purst t purst t rpd t rvalid v v th rese t rese t cat150xx9 cat150xx1 rpd t fi g ure 1. reset output timin g
CAT15008, cat15016 doc. no. 1125 rev. a 6 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice figure 2 shows the maximum pulse duration of negative-going v cc transients that do not cause a reset condition. as the amplitude of the transient goes further below the threshold (increasing v th - v cc ), the maximum pulse duration decreases. in this test, the v cc starts from an initial voltage of 0.5v above the threshold and drops below it by the amplitude of the overdrive voltage (v th - v cc ). embedded eeprom description the CAT15008/16 devices support the serial peripheral interface (spi) bus protocol, modes (0,0) and (1,1). the device contains an 8-bit instruction register. the instruction set and associated op-codes are listed in table 1. reading data stored in the CAT15008/16 is accom? plished by simply providing the read command and an address. writing to the CAT15008/16, in addition to a write command, address and data, also requires enabling the device for writing by first setting certain bits in a status register, as will be explained later. after a high to low transition on the cs input pin, the CAT15008/16 will accept any one of the six instruction op-codes listed in table 1 and will ignore all other possible 8-bit combinations. the communication protocol follows the timing from figure 3. figure 2. maximum transient duration without causing a reset pulse vs. overdrive voltage table 1: instruction set instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory write 0000 0010 write data to memory figure 3. synchronous data timing note: dashed line = mode (1, 1) - - - - - - valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so t ri t fi transie n t du r ation [s] reset overdrive v th - v cc [mv] t amb = 25oc cat150xxm cat150xxz
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 7 doc. no. 1125 rev. a characteristics subject to change without notice status register the status register, as shown in table 2, contains a number of status and control bits. the rdy (ready) bit indicates whether the device is busy with a write operation. this bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. for the host, this bit is read only. the wel (write enable latch) bit is set/reset by the wren/wrdi commands. when set to 1, the device is in a write enable state and when set to 0, the device is in a write disable state. the bp0 and bp1 (block protect) bits determine which blocks are currently write protected. they are set by the user with the wrsr command and are non-volatile. the user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to table 3. the protected blocks then become read-only. the wpen (write protect e nable) bit acts as an enable for the wp pin. hardware write protection is enabled when the wp pin is low and the wpen bit is 1. this condition prevents writing to the status register and to the block protected sect ions of memory. while hardware write protection is active, only the non-block protected memory can be written. hardware write protection is disabled when the wp pin is high or the wpen bit is 0. the wpen bit, wp pin and wel bit combine to either permit or inhibit write operations, as detailed in table 4. table 2. status register 7 6 5 4 3 2 1 0 wpen 0 0 0 bp1 bp0 wel rdy table 3. block protection bits status register bits bp1 bp0 array address protected protection 0 0 none no protection 15008: 0300-03ff 0 1 15016: 0600-07ff quarter array protection 15008: 0200-03ff 1 0 15016: 0400-07ff half array protection 15008: 0000-03ff 1 1 15016: 0000-07ff full array protection table 4. write protect enable operation wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
CAT15008, cat15016 doc. no. 1125 rev. a 8 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice write operations the CAT15008/16 device powers up into a write disable state. the device contains a write enable latch (wel) which must be set before attempting to write to the memory array or to the status register. in addition, the address of the memory locati on(s) to be written must be outside the protected area, as defined by bp0 and bp1 bits from the status register. write enable and write disable the internal write enable latch and the corresponding status register wel bit are set by sending the wren instruction to the CAT15008/16. care must be taken to take the cs input high after the wren instruction, as otherwise the write enable latch will not be properly set. wren timing is illustrated in figure 4. the wren instruction must be sent prior any write or wrsr instruction. the internal write enable latch is reset by sending the wrdi instruction as shown in figure 5. disabling write operations by resetting the wel bit, will protect the device against inadvertent writes. figure 4. wren timing note: dashed line = mode (1, 1) - - - - - - figure 5. wrdi timing note: dashed line = mode (1, 1) - - - - - - sck si cs so 00000 110 high impedance sck si cs so 00000 100 high impedance
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 9 doc. no. 1125 rev. a characteristics subject to change without notice sck si so 00 00 00 10 d7 d6 d5 d4 d3 d2 d1 d0 012345678 2122232425262728293031 cs opcode * please check the byte address table (table 5) data in high impedance byte address* a n a 0 byte write once the wel bit is set, the user may execute a write sequence, by sending a write instruction, a 16-bit address and data as shown in figure 6. only 10 significant address bits are used by the CAT15008 and 11 by the cat15016. the rest are don?t care bits, as shown in table 5. internal programming will start after the low to high cs transition. during an internal write cycle, all commands, except for rdsr (read status register) will be ignored. the rdy bit will indicate if the internal write cycle is in progress (rdy high), or the the device is ready to accept commands (rdy low). page write after sending the first data byte to the CAT15008/16, the host may continue sending data, up to a total of 32 bytes, according to timing shown in figure 7. after each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. if during this process the end of page is exceeded, then loading will ?roll over? to the first byte in the page, thus possibly overwriting previoualy loaded data. following completion of the write cycle, the CAT15008/16 is automatically returned to the write disable state. table 5. byte address device address significant bits address don't care bits # address clock pulse CAT15008 a9 - a0 a15 - a10 16 cat15016 a10 - a0 a15 - a11 16 figure 6. byte write timing note: dashed line = mode (1, 1) - - - - - - figure 7. page write timing note: dashed line = mode (1, 1) - - - - - - sck si so 00 00 00 10 byte address* data byte 1 012345678 212223 24-31 32-39 data byte 2 data byte 3 data byte n cs opcode 7..1 0 24+(n-1)x8-1..24+(n-1)x8 24+nx8-1 data in high impedance a n a 0 *please check the byte address table. (table 5)
CAT15008, cat15016 doc. no. 1125 rev. a 10 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice write status register the status register is wr itten by sending a wrsr instruction according to timing shown in figure 8. only bits 2, 3 and 7 can be written using the wrsr command. write protection the write protect (wp ) pin can be used to protect the block protect bits bp0 and bp1 against being inadvertently altered. when wp is low and the wpen bit is set to ?1?, write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the stat us register. if the internal write cycle has already been initiated, wp going low will have no effect on any writ e operation to the status register. the wp pin function is blocked when the wpen bit is set to ?0?. the wp input timing is shown in figure 9. figure 8. wrsr timing note: dashed line = mode (1, 1) - - - - - - figure 9. wp timing note: dashed line = mode (1, 1) - - - - - - 01 23 45678 10 911121314 sck si msb high impedance data in 15 so cs 7 6 5 4 3 2 10 0000000 1 opcode cs sck wp wp t wps t wph
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 11 doc. no. 1125 rev. a characteristics subject to change without notice sck si so 0000001 1 byte address* 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 * please check the byte address table (table 5). cs data out msb high impedance a n a 0 opcode read operations read from memory array to read from memory, the host sends a read instruction followed by a 16-bit address (see table 5 for the number of significant address bits). after receiving the last address bit, the CAT15008/16 will respond by shifting out data on the so pin (as shown in figure 10). sequentially stored data can be read out by simply continuing to run the clock. the internal address pointer is automatically incremented to the next higher address as data is shifted out. after reaching the highest memory address, the address counter ?rolls over? to the lowest memory address, and the read cycle can be continued indefinitely. the read operation is terminated by taking cs high. read status register to read the status register , the host simply sends a rdsr command. after receiving the last bit of the command, the CAT15008/16 will shift out the contents of the status register on the so pin (figure 11). the status register may be read at any time, including during an internal write cycle. figure 10. read timing note: dashed line = mode (1, 1) - - - - - - figure 11. rdsr timing note: dashed line = mode (1, 1) - - - - - - 01 2345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 cs 00 0 00 1 01
CAT15008, cat15016 doc. no. 1125 rev. a 12 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice package outlines 8-lead 150 mil soic (w) notes: (1) all dimensions are in millimeters. (2) complies with jedec specification ms-012 dimensions. symbol a1 a b c d e e1 h l min 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.25 0.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 bsc 0.50 1.27 q1 0 8 e e1 d a1 e l q1 c b h x 45 a for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
CAT15008, cat15016 ? 2007 catalyst semiconductor, inc. 13 doc. no. 1125 rev. a characteristics subject to change without notice package marking 8-lead soic 150xxzwi 4yywwa csi = catalyst semiconductor, inc. xx = device code (see marking code table below) z = supervisory output code (see marking code table below) i = temperature range yy = production year ww = production week a = product revision 4 = lead finish nipdau device marking codes xx 15008 08 15016 16 supervisory marking codes z output active low 9 output active high 1
CAT15008, cat15016 doc. no. 1125 rev. a 14 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice ordering information notes: (1) all packages are rohs-comp liant (lead-free, halogen-free). (2) the standard lead finish is nipd au pre-plated (ppf) lead frames. (3) the device used in the above example is a CAT150089swi-gt3 (8kb eeprom, with active low cmos reset output, with a reset thr eshold between 2.85v - 3.00v, soic package, indust rial temperature, nipdau, tape and reel. (4) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. prefix device # suffix cat 15008 9 s w i - g t3 company id package w: soic reset threshold voltage l: 4.50v ? 4.75v m: 4.25v ? 4.50v j: 3.89v ? 4.10v t: 3.00v ? 3.15v s: 2.85v ? 3.00v r: 2.55v ? 2.70v z: 2.25v ? 2.38v lead finish g: nipdau temperature range i = industrial (-40oc to 85oc) product type with memory density 15008: 8-kb eeprom 15016: 16-kb eeprom supervisor output type 9: cmos active low 1: cmos active high tape & reel t: tape & reel 3: 3000 units / reel
revision history date rev. reason 01/15/07 a initial issue copyrights, trademarks and patents trademarks and register ed trademarks of catalyst semiconductor include each of the following: beyond memory?, dpp?, ezdim?, minipot?, and quad-mode? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or gu arantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any ot her application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or se rvice described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: 1125 fax: 408.542.1200 revision: a www.catsemi.com issue date: 01/15 / 07

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